As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed by portions of the vertical semiconductor fin extending from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device.
The gate structures of FinFET devices can be formed using various techniques. For example, a FinFET gate structure can be fabricated using a “gate-last” process, which involves, for example, forming a dummy gate structure on a vertical semiconductor fin, fabricating other FinFET device elements (e.g., source/drain regions), and then replacing the dummy gate structure with a metal gate structure. In one conventional process, a dummy gate structure is a sacrificial structure which comprises a dummy gate oxide layer formed on a channel region of the vertical semiconductor fin, and a dummy gate electrode layer formed over the dummy gate oxide layer. The dummy gate structure is subsequently removed and replaced with a metal gate structure using a replacement metal gate (RMG) process.
With RGM, metal gate structures for FinFET devices are formed after other components (e.g., source/drain regions) of the FinFET devices are formed, so that the metal gate structures are not subjected to various potentially damaging processing steps, for example high-temperature anneals, which are performed in previous steps prior to gate replacement. For advanced FinFET technologies, it is important to prevent etch damage to FinFET device structures (e.g., gate spacers, channel region of vertical semiconductor fin structure, ILD (interlayer dielectric layer, etc.) when etching the sacrificial materials to remove the dummy gate structures.